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| MM74HC157 Quad 2-Input Multiplexer September 1983 Revised February 1999 MM74HC157 Quad 2-Input Multiplexer General Description The MM74HC157 high speed Quad 2-to-1 Line data selector/Multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. This device consists of four 2-input digital multiplexers with common select and STROBE inputs. When the STROBE input is at logical "0" the four outputs assume the values as selected from the inputs. When the STROBE input is at a logical "1" the outputs assume logical "0". The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Typical propagation delay: 14 ns data to any output s Wide power supply range: 2-6V s Low power supply quiescent current: 80 A maximum (74HC Series) s Fan-out of 10 LS-TTL loads s Low input current: 1 A maximum Ordering Code: Order Number MM74HC157M MM74HC157SJ MM74HC157MTC MM74HC157N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Function Table Inputs Strobe H L L L L H = HIGH Level, L = LOW Level X = Irrelevant Output A X L H X X B X X X L H Y L L H L H Select X L L H H Top View (c) 1999 Fairchild Semiconductor Corporation DS005314.prf www.fairchildsemi.com MM74HC157 Logic Diagram www.fairchildsemi.com 2 MM74HC157 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns -40 +85 C 2 0 Max 6 VCC Units V V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 Units V V V V V V V V V V V V V V V V A A VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC157 AC Electrical Characteristics VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH Parameter Maximum Propagation Delay, Data to Output Maximum Propagation Delay, Select to Output Maximum Propagation Delay, Strobe to Output 12 18 ns 14 20 ns Conditions Typ 14 Guaranteed Limit 20 Units ns AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay, Select to Output tPHL, tPLH Maximum Propagation Delay, Strobe to Output tTLH, tTHL Maximum Output Rise and Fall Time CIN CPD Maximum Input Capacitance Power Dissipation Capacitance (Note 5) (per Multiplexer) 57 pF 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 63 13 11 63 13 11 58 12 10 30 8 7 5 125 25 21 125 25 21 115 23 20 75 15 13 10 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 158 32 27 158 32 27 145 29 25 95 19 16 10 186 37 32 186 37 32 171 34 29 110 22 19 10 Units ns ns ns ns ns ns ns ns ns ns ns ns pF tPHL, tPLH Maximum Propagation Delay, Data to Output Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC. www.fairchildsemi.com 4 MM74HC157 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HC157 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 MM74HC157 Quad 2-Input Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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